Flat Display Apparatus and Control Circuit and Method for Controlling the same

ABSTRACT

In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromthe prior Taiwanese Patent Application No. 097103014, filed Jan. 25,2008, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a flat display apparatus, a controlcircuit and a control method employed therein, especially a flat displayapparatus using different signals to drive horizontal scanning lines ofthe flat display device, a control circuit and a control method forcontrolling the flat display apparatus

2. Description of the Related Art

Flat display devices such as liquid crystal displays have been widelyused in all kinds of electronic devices. With the extending demands ofcustomers, sizes of display screen of the flat displays have developedfrom small size originally employed in portable computers to middle sizeemployed in desktop computers, and then to large size employed in familycinema gradually. It is important to maintain a displaying uniformity ofa whole screen with the increasing size of the display screen.

Following the increasing size of the display device, amount of displayunit defined in the display device for displaying image called as pixelis also increasing. Even a refresh frequency of an image does notincrease, a transition of voltage level of scanning signal must befaster to satisfy a displaying demand because of the increasing pixels.However, the faster transition of voltage level results in a feed-thougheffect of a capacitor generated by a capacitive coupling effect, whichcauses a stored voltage of the pixel changed. Therefore, the displayinguniformity is challenged in both horizontal and vertical directions.

Referring to FIG. 7, a block diagram of a typical liquid crystal displayis shown. The liquid crystal display 10 includes a control circuit 100,a data driving module 110, a gate driving module 120, and a displaypanel 130. The control circuit 100 receives display data and all kindsof control data needed for displaying. The control circuit 100transforms the display data and a part of the control data to firstsignals needed by the data driving module 110, and outputs the firstsignals to the data driving module 110. The control circuit 100transforms the other part of the control data to second signals neededby the gate driving module 120 and outputs the second signals to thegate driving module 120. The data driving module 110 drives the datalines 112, 114 according to the received first signals, and the gatedriving module 120 drives the scanning lines 122, 124 according to thereceived second signals. In the display panel 130, each pixel 132denoted by a dotted frame is formed at the intersections of the dataline 112, 114 and the scanning line 122, 124

Referring to FIG. 8A and FIG. 8B, FIG. 8A is an equivalent circuitdiagram of a pixel 132 of the liquid crystal display 10 in FIG. 7, andFIG. 8B is a signal wave diagram of a driving signal employed in thegate driving module 120 in FIG. 7 for driving the gate line 122. Thepixel 132 includes a thin film transistor 200, a liquid crystalcapacitor C_(LC), a storage capacitor C_(S), and a parasitic capacitorC_(GD). The gate electrode 200 c of the thin film transistor 200 iselectrically coupled to the scanning line 122. The source electrode 200a of the thin film transistor 200 is electrically coupled to the dataline 114. The drain electrode 200 b of the thin film transistor 200 iselectrically coupled to a terminal of the liquid crystal capacitorC_(LC), a terminal of the storage capacitor C_(S), and a terminal of theparasitic capacitor C_(GD). The other terminal of the liquid crystalcapacitor C_(LC) and the other terminal of the storage capacitor C_(S)are configured for receiving a common voltage V_(COM). The otherterminal of the parasitic capacitor C_(GD) is electrically connected tothe scanning line 122.

As shown in FIG. 8B, when the scanning signal is provided to thescanning line 122, after a low level voltage Vgl changes to reach a highlevel voltage Vgh via a rising edge RE, the thin film transistor 200 isturned on due to the high level voltage Vgh been provided to the gateelectrode 200 c. On the contrary, when the high level voltage Vghchanges to reach a low level voltage Vgl via a falling edge FE, the thinfilm transistor 200 is turned off due to the decreasing voltage providedto the gate electrode 200 c. However, a fast transition of the voltageat the rising edge RE and the falling edge FE results in a capacitivecoupling effect of the parasitic capacitor C_(GD) between the gate 200 cand drain electrodes 200 b of the thin film transistor 200. Thus, avoltage maintain at the drain electrode 200 b is changed to make apotential crossing the liquid crystal capacitor C_(LC) deviated from aoriginal pre-stored potential. A difference of the actual potentialcrossing the liquid crystal capacitor C_(LC) and the original pre-storedpotential is call as a feed-though voltage V_(f).

If the feed-though voltages V_(f) in all the display panel 130 are same,a problem caused by the feed-though voltage V_(f) can easily be solved.However, in fact, the feed-though voltages V_(f) respectivelycorresponding to each pixel in all the display panel 130 are different.In the horizontal direction, the difference of the feed-though voltagesV_(f) are mainly caused by a signal delay of the scanning lines whichmake an operation of turning off the thin film transistors 200 arrangedin a same scanning line inconsistent. In the vertical direction, thedifference of the feed-though voltages V_(f) are mainly caused by avoltage drop of a current and a resistance. When the gate high levelvoltage Vgh and the gate low level voltage Vgl are provided to thedisplay panel 130, the wires layout made from different conductinglines, such as metal lines or thin film lines, generate voltage dropthereof. In any case, when signals transmit along the conducting lines(gate lines), a voltage difference (Vgh−Vgl) of the gate lines isgradually decreased with the signals been transmitted downward along thegate lines. The feed-through voltage V_(f) can be obtained according tofollowing formula:

$V_{f} = {( {V_{gh} - V_{gl}} )\frac{C_{GD}}{C_{S} + C_{LC} + C_{{GD},{ON}}}}$

wherein C_(GD,ON) is a parasitic capacitor of the conductive thin filmtransistor 200. That is, if the voltage difference (Vgh−Vgl) of the gatelines varies in the vertical direction, the feed-through voltage V_(f)is inevitably changes following the variation of the voltage difference.

To solve the above described problems, many solutions are provided.These solutions are all aimed at solving the uneven display generated bythe feed-through effect of the scanning lines arranged in the horizontaldirection. In fact, these solutions did achieve some improvement in amanner, such as U.S. Pat. No. 6,359,607, U.S. Pat. No. 6,867,760, U.S.Pat. No. 7,027,024 and US published application No. 2006/0077163, et al.However, after experimental proof, these solutions can only solve aproblem of uneven display in the horizontal direction and can not solvethe uneven display in the vertical direction. The following chart 1shows a plurality of voltage differences (Vgh−Vgl) at correspondingareas in a 40 inches LCD panel (it is assumed that the 40 inches LCDpanel is divided into sixteen areas arranged as a 4×4 matrix) whennormal signals are provided to the 40 inches LCD panel.

CHART 1 5.99 6.27 6.31 6.25 6.00 6.27 6.31 6.25 6.00 6.26 6.31 6.24 6.026.28 6.33 6.28

After employing the technology provided by the U.S. Pat. No. 6,359,607,the voltage differences (Vgh−Vgl) at corresponding areas of the same LCDpanel are shown in Chart 2.

CHART 2 6.23 6.29 6.35 6.31 6.26 6.32 6.37 6.33 6.26 6.32 6.37 6.33 6.276.33 6.37 6.37

To sum up, after using the technology provided by the U.S. Pat. No.6,359,607, the voltage differences (Vgh−Vgl) in the horizontal directionmay be improved in a manner. However, the voltage differences (Vgh−Vgl)in the vertical direction is not only improved, but also become largerthan that using original technology in a manner. In other words, afterusing the technology, the uniformity of displaying in the verticaldirection becomes worse.

SUMMARY OF THE INVENTION

In one aspect, an exemplary control method for a flat display apparatusis provided. The flat display apparatus includes a plurality of gatedriving units each of which controls the operation of a scan line. Themethod comprises providing a first gate high level voltage signal and asecond gate high level voltage signal to the gate driving units suchthat the first and second gate high level voltage signals are used asvoltage signals transmitted to corresponding scan lines. The first andsecond gate high level voltage signals respectively include a fallingedge with a slope. A duration time of the falling edge of the first gatehigh level voltage signal is longer than that of the falling edge of thesecond gate high level voltage signal.

In the exemplary embodiment, the above described control method firstlygenerate a original gate high level voltage signal with fixed frequency,a first chamfering control signal, and a second chamfering controlsignal, then generate the first gate high level voltage signal bygradually decreasing the voltage of the original gate high level voltagesignal in an duty cycle of the first chamfering control signal. thesecond gate high level voltage signal can similarly be generated bygradually decreasing the voltage of the original gate high level voltagesignal in another duty cycle of the second chamfering control signal.The duty cycle of the first chamfering control signal is longer thanthat of the second chamfering control signal.

In another aspect, an exemplary control circuit of a flat displayapparatus is provided. The flat display apparatus employs an enablesignal to turn on a plurality of scanning lines thereof. The controlcircuit includes a signal generating module, a first gate driving unit,a second gate driving unit. The signal generating module is configuredfor generating a first gate high level voltage signal and a second gatehigh level voltage signal. The first gate driving unit is electricallycoupled to the signal generating module and configured for receiving thefirst gate high level voltage signal as a voltage signal for providingto one of the scanning lines. The second gate driving unit iselectrically coupled to the signal generating module and configured forreceiving the second gate high level voltage signal as a voltage signalfor providing to other one of the scanning lines. The first gate drivingunit and the second gate driving unit are electrically coupled to eachother so as to sequentially transmit the enable signal. The first gatehigh level voltage signal and second gate high level voltage signalrespectively include a falling edge with a slope. A duration time of thefalling edge of the first gate high level voltage signal is longer thanthat of the falling edge of the second gate high level voltage signal.

In the exemplary embodiment, the above described signal generatingmodule includes the chamfering control signal generating unit and gatehigh level voltage signal generating unit. The chamfering control signalgenerating unit is used for generating the first chamfering controlsignal and the second chamfering control signal with different dutycycles. The gate high level voltage signal generating unit iselectrically coupled to the chamfering control signal generating unit soas to receive the first chamfering control signal and the secondchamfering control signal and respectively change a falling edge of theoriginal gate high level voltage signal to generate the first and secondgate high level voltages according to the first and second chamferingcontrol signal.

Still in another aspect, an exemplary flat display apparatus isprovided. The flat display apparatus includes a display panel, aplurality of data driving units, and a control circuit. The displaypanel includes a plurality of data lines, a plurality of scanning lines,and a plurality of pixel units. The data lines are paralleled extendedon the display panel along a first direction for transmitting image dataused for display image. The scanning lines are paralleled extended onthe display panel along a second direction. The pixel units arepositioned adjacent the intersections of the data lines and the scanninglines. The scanning lines are configured for turning on/off the pixelunits. The data driving units are respectively electrically coupled tothe data lines for providing the image data used for displaying image.The control circuit includes a signal generating module, a first gatedriving unit, and a second gate driving unit. The signal generatingmodule is configured for generating a first gate high level voltagesignal and a second gate high level voltage signal. The first gatedriving unit is electrically coupled to the signal generating module andconfigured for receiving the first gate high level voltage signal as avoltage signal for providing to one of the scanning lines. The secondgate driving unit is electrically coupled to the signal generatingmodule and configured for receiving the second gate high level voltagesignal as a voltage signal for providing to other one of the scanninglines. The first gate driving unit and the second gate driving unit areelectrically coupled to each other so as to sequentially transmit theenable signal. The first gate high level voltage signal and second gatehigh level voltage signal respectively include a falling edge with aslope. A duration time of the falling edge of the first gate high levelvoltage signal is longer than that of the falling edge of the secondgate high level voltage signal.

Aforementioned embodiments of the present invention provide differentdriving signals to different gate driving units, and the falling edgeshave a same slope and a different duration time. Thus differentcompensations for different feed-through voltages are provided accordingto different position of the display panel. An experiment proves thatthis method can provides a uniform display in the vertical direction.

Other objectives, features and advantages of the touch panel device willbe further understood from the further technological features disclosedby the embodiments of display system wherein there are shown anddescribed preferred embodiments of this flat display apparatus, simplyby way of illustration of modes best suited to carry out the presentinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features and advantages of the various embodimentsdisclosed herein will be better understood with respect to the followingdescription and drawings, in which like numbers refer to like partsthroughout, and in which:

FIG. 1 is circuit block diagram of a flat display apparatus according toa first embodiment.

FIG. 2 is a signal wave diagram showing two different gate high levelvoltages signals.

FIG. 3 is a flow chart of generating gate high level voltage signalswith different duration time according to an exemplary embodiment.

FIG. 4 is a schematic diagram illustrating generating gate high levelvoltage signals having falling edges with different duration time.

FIG. 5 is a circuit block of a signal generating module according to anexemplary embodiment.

FIG. 6 is a circuit block of a control circuit according to analternative embodiment.

FIG. 7 is a circuit block diagram of a conventional liquid crystaldisplay.

FIG. 8A is an equivalent circuit diagram of a pixel of the liquidcrystal display of FIG. 7.

FIG. 8B is a signal wave diagram of a driving signal employed in a gatedriving module of FIG. 7 for driving a scanning line.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

Referring to FIG. 1, a block diagram of a flat display apparatus 30according to a first embodiment is shown. In the exemplary embodiment,the flat display apparatus 30 includes a display panel 300, a datadriving module 31, and a control circuit 32. A plurality of data lines340, 342, 344, a plurality of scanning lines 350, 352, 354 and aplurality of pixel units 360, 362, 364 positioned adjacent theintersections of the data lines 340, 342, 344 and the scanning lines250, 352, 354 are all arranged in the display panel 300.

The data driving module 31 includes a plurality of data driving unit310, 312 and 314. The control circuit 32 includes a plurality of gatedriving units 320, 322, 324 and a signal generating module 330. Anequivalent circuit of each pixel unit of the pixel units 360, 362, 364is shown in FIG. 8A. The number of the above described data lines,scanning lines, pixel units, data driving units, gate driving units andsignal generating module is illustrated to conveniently describe thisembodiment but not limited.

As showing in the FIG. 1, the data lines 340, 342, and 344 areparalleled extended on the display panel 300 along a special direction,hereafter call as a first direction. The scanning lines 350, 352 and 354are paralleled extended on the display panel 300 along another specialdirection, hereafter call as a second direction. The data lines 340,342, 344 are used to transmit image data configured for displayingimage. The scanning lines 350, 352, 354 are respectively used totransmit scanning signals configured for turning on/off the pixel units360, 362, 364.

When the scanning lines 350, 352, 354 are used to transmit scanningsignals configured for turning on the pixel units 360, 362, 364, thegate driving units 320, 322, 324 need to provide corresponding gate highlevel voltage signals to the scanning lines 350, 352, 354. In theexemplary embodiment, the gate high level voltage signals provided bythe gate driving units 320, 322, 324 and enable signals for controllingthose gate driving units 320, 322, 324 to be actuated are generated bythe signal generating module 330.

The enable signals are sequentially transmitted along a direction fromthe gate driving unit 320 to the gate driving units 322, 324 andgradually far from the signal generating module 330. As soon as anenable signal is transmitted to start up one of the gate driving units,such as the gate driving unit 322, the gate driving unit permits thereceived gate high level voltage signals to be passed therefrom andtransmitted to the corresponding scanning line, such as the scanningline 352. In addition, according to feed-through effect with differentdegrees, the signal generating module 330 generates at least twodifferent gate high level voltage signals and provides to the gatedriving units 320, 322, 324.

Referring to FIG. 2 together, a signal wave diagram of the two differentgate high level voltage signals is shown. Operating periods of the gatehigh level voltage signals 400 and 410 are substantially same. The gatehigh level voltage signals 400 and 410 have two falling edges 400 a and410 a with inclination respectively. The inclination of the falling edge400 a has a slope the same as that of the inclination of the fallingedge 410 a. However, a duration time of the falling edge 400 a of thegate high level voltage signals 400 is different from that of thefalling edge 410 a of the gate high level voltage signals 410. In theexemplary embodiment, the duration time of the falling edge 400 a is t1,the duration time of the falling edge 410 a is t2 and t1 is longer thant2. Because the feed-through voltages V_(f) respectively correspondingto the pixel units of the display panel 300 are different.

Particularly in the vertical direction, the difference of thefeed-through voltages V_(f) are mainly caused by a voltage drop of acurrent and a resistance. When the gate high level voltage Vgh and thegate low level voltage Vgl are provided to the display panel 300, andtransmitted along metal lines or thin film lines (on the display panel300), the voltage difference (Vgh−Vgl) of the gate lines is graduallydecreased with the signals being transmitted downward along theconductive lines 326 in the control circuit 32. The feed-through voltageV_(f) can be obtained according to following formula:

$V_{f} = {( {V_{gh} - V_{gl}} )\frac{C_{GD}}{C_{S} + C_{LC} + C_{{GD},{ON}}}}$

wherein, C_(GD,ON) is a parasitic capacitor of a conductive thin filmtransistor 200 of FIG. 8A. Because the gate driving unit far from thesignal generating module 330 (as showing in FIG. 1, a distance betweenthe gate driving unit 322 and the signal generating module 330 isfarther than the distance between the gate driving unit 320 and thesignal generating module 330) has a lesser voltage difference (Vgh−Vgl),the corresponding feed-through voltage V_(f) is decreased. Thus, thehigh level voltage signal 400 a having a falling edge with the longerduration time, hereafter call as a first high level voltage signal, isprovided to a gate driving unit close to the signal generating module330. The high level voltage signal 410 a having a falling edge with theshorter duration time, hereafter call as a second high level voltagesignal, is provided to a gate driving unit far away from the signalgenerating module 330.

The following description will explain how to generate the gate highlevel voltage signals with different duration time. Referring to FIG. 3,a flow chart of generating gate high level voltage signals withdifferent duration time is shown according to an exemplary embodiment.

Step S500 is generating an original gate high level voltage signaldefined as a basis. Step S510 is generating a plurality of chamferingcontrol signals, each of which has a different duty cycle. Step S520 isgenerating a plurality of different gate high level voltage signals byrespectively gradually decreasing the voltage of the original gate highlevel voltage signal in the different duty cycles of the correspondingchamfering control signals.

The original gate high level voltage signal generated in step S500 canbe denoted by any one of the original gate high level voltage signals600, 610, 620 as showing in FIG. 4. An amplitude of the original gatehigh level voltage signal is vibrated between the gate high levelvoltage Vgh and the gate low level voltage Vgl. An exemplary chamferingcontrol signals referred in the step S510 can be denoted by chamferingcontrol signals 600 a, 610 a, 620 a as showing in FIG. 4. The chamferingcontrol signals 600 a, 610 a and 620 a respectively have a differentduty cycle t₃, t₄ and t₅.

As showing in FIG. 4, the original gate high level voltage signals 600,610 and 620 respectively correspond to the chamfering control signals600 a, 610 a and 620 a.

The voltage of the original gate high level voltage signal 600 isgradually decreased in the duty cycle t₃ of the chamfering controlsignal 600 a by a fixed slope to form a gate high level voltage signal600 b with a falling edge 601. Similarly, the voltage of the originalgate high level voltage signal 610 is gradually decreased in the dutycycle t₄ of the chamfering control signal 610 a by the fixed slope toform a gate high level voltage signal 610 b with a falling edge 611, andthe voltage of the original gate high level voltage signal 620 isgradually decreased in the duty cycle t₅ of the chamfering controlsignal 620 a by the fixed slope to form a gate high level voltage signal620 b with a falling edge 621.

Although in the exemplary embodiment of FIG. 4, the corresponding gatehigh level voltage signals are generated by using a plurality oforiginal high level voltage signals, in an alternative embodiment, thecorresponding gate high level voltage signals can also be generated in amanner as showing in FIG. 5. That is, only one original high levelvoltage signal is generated and transmitted to a plurality of circuitsto generate different gate high level voltage signals after the originalhigh level voltage signal being processed respectively in accordancewith corresponding chamfering control signals.

Referring to FIG. 5, a block diagram of an exemplary signal generatingmodule 70 is shown. The signal generating module 70 includes achamfering control signal generating unit 700 and a gate high levelvoltage signal generating unit 710. The gate high level voltage signalgenerating unit 710 includes an original signal generating unit 712, anda plurality of processing circuits 714, 716 . . . 718. The chamferingcontrol signal generating unit 700 is configured to generate a pluralityof different chamfering control signals YC1,YC2 . . . YCn and providethe chamfering control signals YC1,YC2 . . . YCn to the gate high levelvoltage signal generating unit 710.

The original signal generating unit 712 is firstly employed to generatean original gate high level voltage signal as showing in FIG. 4 andrespectively provide the original gate high level voltage signal to theprocessing circuits 714, 716 . . . 718. At the same time, the processingcircuits 714, 716 . . . 718 respectively process the received thechamfering control signals YC1,YC2 . . . YCn incorporated with theoriginal gate high level voltage signal to obtain corresponding highlevel voltage signals VG1, VG2 . . . VGn.

Understandably, in an alternative embodiment, the original gate highlevel voltage signal employed in the gate high level voltage signalgenerating unit 710 can also be generated by other circuit of the flatdisplay device 30 and then provided to the gate high level voltagesignal generating unit 710. The above described exemplary circuit isgiven by way of example, and not limitation.

Except the above described circuit and method of the exemplaryembodiments, a plurality of detailed adjusting parts of an alternativeembodiment of the present invention are also provided. For example,referring to FIG. 6, a block diagram of an exemplary control circuit 82according to an alternative embodiment is shown. In the exemplaryembodiment, the control circuit 82 includes a signal generating module830 and a plurality of gate driving units 820, 822, 824 et al. Thesignal generating module 830 provides different gate high level voltagesignals to the gate driving units 820, 822, 824 via a respectiveconducting line. In FIG. 1, the gate driving units 320, 322, 324 areelectrically coupled to the signal generating module 300 via a sameconducting line or a same electronic route. Thus the gate high levelvoltage signals provided by the signal generating module 330 can all bereceived by each of the gate driving units 320, 322 and 324.

Comparing with FIG. 1, the gate driving units 820, 822 and 824 of thecontrol circuit 82 showing in FIG. 6 are respectively electricallyconnected to the signal generating module 830 via different conductinglines, thus each gate high level voltage signal can be independentlytransmitted to the corresponding gate driving unit.

In further alternative embodiments, for example, a plurality of gatedriving units can be defined as a gate driving group for using a samegate high level voltage signal. The chamfering control signal generatingunit 700 showing in FIG. 5 can also serially output the chamferingcontrol signals YC1, YC2 . . . YCn in a certain order. A circuit designlayout of the signal generating module the can also be adjusted as longas the essential technology of the present invention can be achieved.

Because the gate high level voltage signals are generated by decreasingwith a same slope in different duration time, the voltage drops in amoment is somewhat changed. Therefore, different compensation effectscan be provided according to the feed-through effect generated by themomentary changed voltage drop.

The above description is given by way of example, and not limitation.Given the above disclosure, one skilled in the art could devisevariations that are within the scope and spirit of the inventiondisclosed herein, including configurations of the circuit and/or designsof the control method. Further, the various features of the embodimentsdisclosed herein can be used alone, or in varying combinations with eachother and are not intended to be limited to the specific combinationdescribed herein. Thus, the scope of the claims is not to be limited bythe illustrated embodiments.

1. A method for controlling a flat display apparatus comprising aplurality of gate driving units, each of which controls the operation ofa scan line in the flat display apparatus, the method comprising:providing a first gate high level voltage signal and a second gate highlevel voltage signal to the gate driving units respectively such thatthe first and second gate high level voltage signals are used as gatevoltage signals transmitted to corresponding scan lines, wherein thefirst and second gate high level voltage signals respectively comprisesa falling edge with a slope, and a duration time of the falling edge ofthe first gate high level voltage signal is longer than a duration timeof the falling edge of the second gate high level voltage signal.
 2. Themethod as claimed in claim 1, wherein the step of providing the firstgate high level voltage signal and the second gate high level voltagesignal comprises: providing the first gate high level voltage signal toa first gate driving unit of the gate driving units; and providing thesecond gate high level voltage signal to a second gate driving unit ofthe gate driving units, wherein an enable signal is employed to actuatethe gate driving units, the gate driving units being arranged in seriesso as to receive the enable signal in order.
 3. The method as claimed inclaim 1, further comprising: generating an original gate high levelvoltage signal with a fixed duty cycle; generating a first chamferingcontrol signal and a second chamfering control signal; generating thefirst gate high level voltage signal by gradually decreasing the voltageof the original gate high level voltage signal in a first duty cycle ofthe first chamfering control signal; generating the second gate highlevel voltage signal by gradually decreasing the voltage of the originalgate high level voltage signal in a second duty cycle of the secondchamfering control signal, wherein the first duty cycle of the firstchamfering control signal is longer than the second duty cycle of thesecond chamfering control signal.
 4. A control circuit of a flat displayapparatus, the control circuit comprising: a signal generating modulefor generating a first gate high level voltage signal and a second gatehigh level voltage signal; a first gate driving unit electricallycoupled to the signal generating module and configured for receiving thefirst gate high level voltage signal as a voltage signal to be providedto one of scanning lines of the flat display apparatus; and a secondgate driving unit electrically coupled to the signal generating moduleand configured for receiving the second gate high level voltage signalas a voltage signal to be provided to other one of the scanning lines,wherein the first gate driving unit and the second gate driving unit areelectrically coupled to each other so as to sequentially be enabled, andthe first gate high level voltage signal and the second gate high levelvoltage signal respectively comprise a falling edge with a slope, aduration time of the falling edge of the first gate high level voltagesignal is longer than a duration time of the falling edge of the secondgate high level voltage signal.
 5. The control circuit as claimed inclaim 4, wherein the signal generating module comprises: a chamferingcontrol signal generating unit configured for generating a firstchamfering control signal and a second chamfering control signal withdifferent duty cycles; and a gate high level voltage signal generatingunit electrically coupled to the chamfering control signal generatingunit for receiving the first chamfering control signal and the secondchamfering control signal, and configured for generating the first gatehigh level voltage signal and second gate high level voltage signal byreferring to a falling edge of an original gate high level voltagesignal which is changed respectively according to the first chamferingcontrol signal and the second chamfering control signal.
 6. The controlcircuit as claimed in claim 4, wherein the first gate driving unit andthe second gate driving unit are electrically coupled to the signalgenerating module via a same electronic route.
 7. The control circuit asclaimed in claim 4, wherein the first gate driving unit and the secondgate driving unit are electrically coupled to the signal generatingmodule via a respective electronic route.
 8. The control circuit asclaimed in claim 4, wherein the signal generating module comprises: achamfering control signal generating unit for generating a plurality ofchamfering control signals; and a gate high level voltage signalgenerating unit comprising: an original signal generating unit forgenerating an original gate high level voltage signal; and a pluralityof processing circuits, each of which receives the original gate highlevel voltage signal and corresponding one of the chamfering controlsignals, wherein, each of the processing circuits respectivelyprocessing the received chamfering control signals incorporated with theoriginal gate high level voltage signal to obtain corresponding one gatehigh level voltage signal.
 9. A flat display apparatus comprising: adisplay panel comprising: a plurality of data lines paralleled extendedon the display panel along a first direction for transmitting image dataused for display image; a plurality of scanning lines paralleledextended on the display panel along a second direction; and a pluralityof pixel units positioned adjacent the intersections of the data linesand the scanning lines, the scanning lines being configured for turningon/off the pixel units; a plurality of data driving units respectivelyelectrically coupled to the data lines for providing image data fordisplaying image; and a control circuit comprising: a signal generatingmodule configured for generating a first gate high level voltage signaland a second gate high level voltage signal; a first gate driving unitelectrically coupled to the signal generating module and configured forreceiving the first gate high level voltage signal as a voltage signalto be provided to one of the scanning lines; and a second gate drivingunit electrically coupled to the signal generating module and configuredfor receiving the second gate high level voltage signal as a voltagesignal to be provided to other one of the scanning lines, wherein thefirst gate driving unit and the second gate driving unit areelectrically coupled to each other so as to sequentially transmit anenable signal for determining which gate driving unit is enabled, andthe first gate high level voltage signal and second gate high levelvoltage signal respectively comprise a falling edge with a slope, aduration time of the falling edge of the first gate high level voltagesignal is longer than that of the falling edge of the second gate highlevel voltage signal.
 10. The flat display apparatus as claimed in claim9, wherein the signal generating module comprises: a chamfering controlsignal generating unit configured for generating a first chamferingcontrol signal and a second chamfering control signal with differentduty cycles; and a gate high level voltage signal generating unitelectrically coupled to the chamfering control signal generating unitfor receiving the first chamfering control signal and the secondchamfering control signal, and configured for generating the first gatehigh level voltage signal and the second gate high level voltage signalby referring to a duration time of a falling edge of the original gatehigh level voltage signal which is changed respectively according to thefirst chamfering control signal and the second chamfering controlsignal.
 11. The flat display apparatus as claimed in claim 9, whereinthe first gate driving unit and the second gate driving unit areelectrically coupled to the signal generating module via a sameelectronic route.
 12. The flat display apparatus as claimed in claim 9,wherein the first gate driving unit and the second gate driving unit areelectrically coupled to the signal generating module via a respectiveelectronic route.
 13. The flat display apparatus as claimed in claim 9,wherein the signal generating module comprises: a chamfering controlsignal generating unit for generating a plurality of chamfering controlsignals; and a gate high level voltage signal generating unitcomprising: an original signal generating unit for generating anoriginal gate high level voltage signal; and a plurality of processingcircuits, each of which receives the original gate high level voltagesignal and corresponding one of the chamfering control signals, wherein,each of the processing circuits respectively processing the receivedchamfering control signals incorporated with the original gate highlevel voltage signal to obtain corresponding one gate high level voltagesignal.